Справка по Verilog

              
Module
module MODID [({PORTID,})];
  [input | output | inout [range] {PORTID,};] 
  [{declaration}]
  [{parallel_statement}]
  [specify_block]
endmodule

range ::= [constexpr : constrexpr]
              
              
Parallel Statements
assign [(strength1, strength0)] WIRID = expr;
initial sequential_statement
always sequential_statement
MODID [#({expr,})] INSTID
  ([{expr,} | {.PORTID(expr),}]);
delay ::=  number | PARID | (expr [, expr[, expr]])

              
              
Sequential Statements
begin[: BLKID  ]
  [{declaration}]
  [{sequential_statement}]
end

if (expr) sequential_statement
[else sequential_statement]

case | casex | casez (expr)
  [{{expr,}}: sequential_statement]
  [default: sequential_statement]
endcase

forever sequential_statement
repeat (expr) sequential_statement
while (expr) sequential_statement
for (lvalue = expr; expr; lvalue = expr)
  sequential_statement

wait (expr) sequential_statement
fork[: BLKID  ]
  [{declaration}]
  [{sequential_statement}]
join

TASKID[({expr,})];
              
              
Declarations
parameter {PARID = constexpr,};
wire [range] {WIRID,};
reg [range] {REGID [range],};
integer {INTID [range],};
time {TIMEID [range],};
real {REALID,};
realtime {REALTIMID,};
task TASKID;
[input | output | inout [range] {ARGID,};] 
  [{declaration}]
begin
  [{sequential_statement}]
end
endtask

function FCTID;
  [input [range] {ARGID,};] 
  [{declaration}]
begin
  [{sequential_statement}]
end
endfunciton

              
              
System Tasks
$display (<list_of_arguments>);
$write (<list_of_arguments>);
$timeformat (<unit_number>, <precision>,
  <suffix_string>, <minimum_field_width>);
$printtimescale (<module_name>);
<file_descriptor> = $fopen (<file_name>,
  <option>);
$fclose(<file_descriptor>);
$fdisplay(<file_descriptor>, <variable>);
$fwrite (<file_descriptor>, <variable>);
$fstrobe (<file_descriptor>, <variable>);
$fmonitor (<file_descriptor>, <variable>);